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WLCSP And Bumping

Unleash the Power of Precision: UTAC's WLCSP with Advanced Bumping for High-Performance Applications

Wafer-Level Chip Scale Packaging (WLCSP) offers compact, cost-effective solutions that enhance performance and thermal efficiency. Combined with precision bumping technology, our WLCSP solutions ensure reliable electrical connections and meet the needs of high-density applications in mobile, automotive, and computing sectors.

State-of-the-Art Wafer Bumping Technologies

Cu Pillar Bump

Package Structure:
0P1M / 1P1M / 2P2M

Bump Structure:
Cu/Ni/SnAg or Cu/SnAg with RDL option

Passivation:
Low temp / High temp PI & PBO including PFAS-free & low stress options

Cu Pillar Bump
Cu Pillar Bump
RDL + Cu Pillar Bump
RDL + Cu Pillar Bump
Lead Free Bump

Package Structure:
1P1M / 2P2M

Bump Structure:
Ni/SnAg with RDL option

Passivation:
Low temp / High temp PI including PFAS-free & low stress options

Lead Free Solder Bump
Lead Free Solder Bump
RDL + Lead Free Solder Bump
RDL + Lead Free Solder Bump
WLCSP Ball Mount

Package Structure:
1P1M / 2P2M / 3P3M (dev) + Ball Mount

RDL & UBM:
Thick RDL & UBM options available

Solder Ball:
SAC405 / SACQ / LF35

Ball Pitch:
300 – 500um

Passivation:
Low temp / High temp PI & PBO including PFAS-free, low stress and thick PBO options

The UTAC Advantage:
Advanced Dicing Technologies

Maximizing Efficiency, Minimizing Waste

Plasma Dicing Benefits

  • Superior die edge quality with high yield (>99.9% AOI).
  • Narrow saw street capability – can significantly increase GDPW and reduce die cost.
  • Allows 100% usage of multi-project wafers (MPW) having different die sizes.
  • Plasma Dicing is high-quality for small die sizes to dicing bumped (solder or CuP) or non-bumped wafers.
Plasma Dicing solutions enhance UTAC's world-class bumping, probe, assembly, test and backend services.
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WLCSP

Fan-in WLCSP with advanced processing capabilities
Fan-in WLCSP with advanced processing capabilities
  • Bump side protection
  • Back side protection
  • Ultrathin WLCSP package
  • TnR finishing with 5S inspection & IR inspection
  • Unit level marking & traceability
Fan-out backend processing service
Fan-out backend processing service
  • Backed processing of fan-out wafers/panels including test
  • Turnkey service with fan-out partner
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World-Class Wafer Probe Process Capability

Wafer Probe Capabilities
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High Parallelism

Up to 32 sites for WLCSP and 1280 for Pad wafers

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Temperature Range

-55˚C to +150˚C

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Frame Probing

Singulated and Fan-Out Wafer

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Blackbox Testing

Security Key Encryption on Wafer Level

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Wafer Size

8″ and 12″

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Software Customization

Support GDBN and PAT* to drive toward zero defect”

 

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Strategic Partnership

Long term partnership with foundries and probe card suppliers.

Probe Card Management

Multiple Probe card Technologies

Cantiveler
Cantiveler
Up to 16 Sites 1752 Pin Counts 40um x 40um Pad Size Bump Pitch 200/400um
Advanced Cantiveler
Advanced Cantiveler
Up to 16 Sites 1052 Pin Counts 40um x 40um Pad Size Bump Pitch 200/400um
Vertical
Vertical
Up to 1280 Sites Pin Counts 26000 Bump Diameter 85um Bump Pitch 200/400um
Micro Spring
Micro Spring
Up to 8 Sites Pin Counts 976 Bump Diameter 100um Bump Pitch 200/400um
Pogo Pin
Pogo Pin
Up to 8 Sites Pin Counts 1456 Bump Diameter 270um Bump Pitch 200/400um
Membrane
Membrane
Up to 8 Sites Pin Counts 1762 Bump Diameter 85um Bump Pitch 200/400um
In House Support

In House Support

Certified In house Probe card maintenance team.

First Level repair stations

Multiple Probe card Technologies

2000x High Power Scope
2000x High Power Scope
Probe Card Analyzer
Probe Card Analyzer
First Level repair stations

World Class Automated Test Process Capability

UTAC OEE System: Traditional to Smart Manufacturing
Automated Wafer Transfer
Automated Test Program Control
Parking Automation
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Have technical questions or want to discuss your next project? Reach out to us.

Contact Our Team